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hn58c65 series 8192-word 8-bit electrically erasable and programmable cmos rom ade-203-374a (z) rev. 1.0 apr. 12, 1995 description the hitachi hn58c65 is a electrically erasable and programmable rom organized as 8192-word 8-bit. it realizes high speed, low power consumption, and a high level of reliability, employing advanced mnos memory technology and cmos process and circuitry technology. it also has a 32-byte page programming function to make its erase and write operations faster. features ? single 5 v supply ? on chip latches: address, data, ce , oe , we ? automatic byte write: 10 ms max ? automatic page write (32 byte): 10 ms max ? fast access time: 250 ns max ? low power dissipation: 20 mw/mhz typ (active) 2.0 mw typ (standby) ? data polling and ready/ busy ? data protection circuity on power on/power off ? conforms to jedec byte-wide standard ? reliable cmos with mnos cell technology ? 10 5 erase/write cycles (in page mode) ? 10 year data retention ordering information type no. access time package hn58c65p-25 250 ns 600 mil 28 pin plastic dip (dp-28) HN58C65FP-25 250 ns 28 pin plastic sop *1 (fp-28d/da) note: 1. t is added to the end of the type no. for a sop of 3.0 mm (max) thickness.
hn58c65 series 2 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v we nc a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 rdy/busy a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss cc (top view) hn58c65p/fp series pin description pin name function a0 ?a12 address input i/o1 ?i/o7 data input/output oe output enable ce chip enable we write enable v cc power (+5 v) v ss ground nc no connection rdy/ busy ready/ busy
hn58c65 series 3 block diagram v v oe ce a4 a0 a5 a12 we cc ss i/o0 i/o7 high voltage generator control logic and timing y decoder x decoder address buffer and latch i/o buffer and input latch y gating memory array data latch rdy/busy mode selection pin mode ce oe we rdy/ busy i/o read v il v il v ih high-z dout standby v ih x *1 x high-z high-z write v il v ih v il high-z to v ol din deselect v il v ih v ih high-z high-z write inhibit x x v ih xv il x high-z data polling v il v il v ih v ol data out (i/o7) note: 1. x = don? care
hn58c65 series 4 absolute maximum ratings parameter symbol value unit supply voltage *1 v cc ?.6 to +7.0 v input voltage *1 vin ?.5 *2 to +7.0 v operating temperature range *3 topr 0 to +70 c storage temperature range tstg ?5 to +125 c notes: 1. with respect to v ss 2. ?.0 v for pulse width 50 ns. 3. including electrical characteristics and data retention. recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input voltage v il ?.3 0.8 v v ih 2.2 v cc + 1 v operating temperature topr 0 70 c
hn58c65 series 5 dc characteristics (ta = 0 to +70 c, v cc = 5 v 10%) parameter symbol min typ max unit test conditions input leakage current i li 2 m av cc = 5.5 v vin = 5.5 v output leakage current i lo 2 m av cc = 5.5 v vout = 5.5/0.4 v v cc current (standby) i cc1 1 ma ce = v ih , ce = v cc v cc current (active) i cc2 8 ma iout = 0 ma duty = 100% cycle = 1 m s at v cc = 5.5 v 25 ma iout = 0 ma duty = 100% cycle = 250 ns at v cc = 5.5 v input low voltage v il ?.3 *1 0.8 v input high voltage v ih 2.2 v cc + 1 v output low voltage v ol 0.4 v i ol = 2.1 ma output high voltage v oh 2.4 v i oh = ?00 m a note: 1. ?.0 v for pulse width 50 ns capacitance (ta = 25 c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance *1 cin 6 pf vin = 0 v output capacitance *1 cout 12 pf vout = 0 v note: 1. this parameter is periodically sampled and not 100% tested. ac characteristics (ta = 0 to +70 c, v cc = 5 v 10%) test conditions ? input pulse levels: 0.4 v to 2.4 v ? input rise and fall time: 20 ns ? output load: 1ttl gate + 100 pf ? reference levels for measuring timing: 0.8 v and 2 v
hn58c65 series 6 read cycle parameter symbol min max unit test conditions address to output delay t acc 250 ns ce = oe = v il , we = v ih ce to output delay t ce 250 ns oe = v il , we = v ih oe to output delay t oe 10 100 ns ce = v il , we = v ih address to output hold t oh 0ns ce = oe = v il , we = v ih oe , ce high to output float *1 t df 090ns ce = v il , we = v ih note: 1. t df is defined at which the outputs archieve the open circuit conditions and are no longer driven. read timing waveform address ce oe we data out high data out valid t acc t ce t oe t oh t df
hn58c65 series 7 write cycle parameter symbol min *1 typ max unit test conditions address setup time t as 0 ns address hold time t ah 150 ns ce to write setup time ( we controlled) t cs 0 ns ce hold time ( we controlled) t ch 0 ns we to write setup time ( ce controlled) t ws 0 ns we hold time ( ce controlled) t wh 0 ns oe to write setup time t oes 0 ns oe hold time t oeh 0 ns data setup time t ds 100 ns data hold time t dh 20ns we pulse width ( we controlled) t wp 200 ns ce pulse width ( ce controlled) t cw 200 ns data latch time t dl 100 ns byte lode cycle t blc 0.30 30 m s byte lode window t bl 100 m s write cycle time t wc 10 *2 ms time to devce busy t db 120 ns write start time t dw 150 ns notes: 1. use this device in longer cycle than this value. 2. t wc must be longer than this value unless polling technique is used. this device automatically completes the internal write operation within this value.
hn58c65 series 8 byte write timing waveform (1) ( we controlled) address ce we oe din rdy/busy t wc t ch t ah t cs t as t wp t oeh t bl t oes t ds t dh t db high-z high-z t dw
hn58c65 series 9 byte write timing waveform (2) ( ce controlled) address ce we oe din rdy/ busy t wc t ah t ws t as t oeh t wh t oes t ds t dh t db t cw t bl t dw high-z high-z
hn58c65 series 10 page write timing waveform (1) ( we controlled) address a0 to a4 we ce oe din rdy/ busy t as t ah t bl t wc t oeh t dh t db t oes t ch t cs wp t dl t blc t t ds t dw high-z high-z address a5 to a12
hn58c65 series 11 page write timing waveform (2) ( ce controlled) address a0 to a4 we ce oe din rdy/ busy t as t ah t bl t wc t oeh t dh t db t oes t wh t ws cw t dl t blc t t ds t dw high-z high-z address a5 to a12
hn58c65 series 12 data polling timing waveform t bl t wc t dw t oes address ce we oe i/o7 t oe din x an an dout x dout x an functional description automatic page write page-mode write feature allows 1 to 32 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 31 bytes can be written in the same manner. each additional byte load cycle must be started within 30 m s of the preceding rising edge of the we . when ce or we is high for 100 m s after data input, the eeprom enters write mode automatically and the input data are written into the eeprom. data polling data polling allows the status of the eeprom to be determined. if eeprom is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from i/o7 to indicate that the eeprom is performing a write operation. rdy/ busy signal rdy/ busy signal also allows the status of the eeprom to be determined. the rdy/ busy signal has high impedance, except in write cycle and is lowered to v ol after the first write signal. at the end of a write cycle, the rdy/ busy signal changes state to high impedance.
hn58c65 series 13 we , ce pin operation during a write cycle, addresses are latched by the falling edge of we or ce and data is latched by the rising edge of we or ce . write/erase endurance and data retention time the endurance is 10 5 cycles in case of the page programming and 3 10 3 cycles in case of byte programming (1% cumulative failure rate). the data retention time is more than 10 years when a device is page- programmed less than 10 4 cycles. data protection 1. data protection against noise on control pins ( ce , oe , we ) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to progam mode by mistake. to prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less in program mode. be careful not to allow noise of a width of more than 20 ns on the control pins. we ce oe 5 v 0 v 5 v 0 v 20 ns max
hn58c65 series 14 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins generated by external circuits (cpu, etc.) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpu is in an unstable state. v cc cpu reset unprogrammable unprogrammable * * *the eeprom should be kept in unprogrammable state during v cc on/off by using cpu reset signal. in addition, when v cc is turned on or off, the input level of on control pins must be held as shown in the table below. ce v cc xx oe xv ss x we xx v cc x: don? care. v cc : pull-up to v cc level v ss : pull-down to v ss level.
hn58c65 series 15 package dimensions hn58c65p series (dp-28) unit: mm 0.51 min 2.54 min 0.25 + 0.11 ?0.05 2.54 ?0.25 0.48 ?0.10 0??15 15.24 1.20 35.60 36.50 max 13.40 14.60 max 1 14 15 28 5.70 max 1.90 max hn58c65fp series (fp-28d) unit: mm 0 ?10 + 0.08 ?0.07 0.17 1.00 ?0.20 0.20 ?0.10 2.50 max 1.27 0.40 + 0.10 ?0.05 8.40 18.30 18.75 max 1.12 max 28 15 1 14 11.80 ?0.30 0.20 m 0.15 1.70
hn58c65 series 16 hn58c65fp series (fp-28da) unit: mm + 0.08 ?0.07 0.17 0.20 ?0.10 3.00 max 1.27 ?0.10 0.40 + 0.10 ?0.05 8.40 18.00 18.75 max 1.27 max 28 15 1 14 11.80 ?0.30 0 ?10 1.00 ?0.20 1.70

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